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Next-Generation Vector Processor Design IV: Simplifying Complex RISC-V Vector Extension Memory Operations
Simplifying Complex RISC-V Vector Extension Memory Operations
簡化RISC-V向量擴展記憶體運算

Dr. Thang Tran, Principal Architect of Andes Technology and veteran of high-performance computing (HPC), on September 30 at 14:00 Taipei Time, for the last in his four-part masterclass series on demystifying the RISC-V Vector Extension.

In this session, Dr. Tran will present a couple of examples using vector instruction vector instructions based on Andes NX27V. He will also discuss NX27V performance, competitive data, tools, and summary.

Sep 30, 2021 02:00 PM in Taipei

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