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Next-Generation Vector Processor Design IV: Simplifying Complex RISC-V Vector Extension Memory Operations
Dr. Thang Tran, Principal Architect of Andes Technology and veteran of high-performance computing (HPC), on September 29 at 9:00 AM Pacific Daylight Time, for the last in his four-part masterclass series on demystifying the RISC-V Vector Extension.

In this session, Dr. Tran will present a couple of examples using vector instruction vector instructions based on Andes NX27V. He will also discuss NX27V performance, competitive data, tools, and summary.

Sep 29, 2021 09:00 AM in Pacific Time (US and Canada)

Webinar is over, you cannot register now. If you have any questions, please contact Webinar host: Andes Technology.